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After permanganate etching, the panel is catalyzed and metallized in an electroless copper bath and panel-plated galvanically to desired thickness Some photovia process practitioners roughen the resin surface mechanically by brushing or liquid horning prior to catalyzing Then, the conductor pattern is formed by dry-film tenting and etching Some manufacturers prefer to use the pattern-plating method for this purpose Very few microvia board manufacturers use direct metallization methods for metallizing holes prior to galvanic plating Several Japanese manufacturers use electroless copper all the way to the desired thickness in panel plating and use a positive electrodeposited (ED) system to achieve fine lines and very small annular rings One important step in microvia hole board fabrication when resin is the dielectric choice, whether the process is photovia or laser via, is the removal of residual catalysts (normally palladium) entrapped in a microporous surface that can cause migration.

The process used in this step is normally a trade secret Photovia processing is now used primarily to fabricate semiconductor chip package substrates because a large number of holes can be formed in one photoexposure and development step However, as mentioned previously, photovia processing suffers more from material shrinkage than laser via processing after full cure, and hole locations tend to move randomly, which makes subsequent registration for patterning difficult Because of this problem, photovia users limit the size of the panel to be much smaller than the usual panel size prevalent in motherboard fabrication to about 400 mm 400 mm Small hole formation is also difficult with the photovia processAs a result, even makers of package substrates are now resorting more to laser via processes as the laser-drilling speed is being improved Photovia process users engaged in mass production are found only in Japan today.

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All photodielectric processes have certain characteristics in general Table 2211 lists the typical processing factors A standard photovia process sequence is described in Fig 2218a..

TABLE 22.11 Four Typical Photodielectrics (Three Epoxy and One Polyimide) and the Processing Parameters for Coating, Exposure, Developing, Desmears, and Metallization Product A Product Material Preclean Apply PID Thickness Drying Exposure Heat bump Development Final cure Roughen Swell Etch Neutralize Metallize: electroless Cu Bake Electroplate L-PID, negative Epoxy Chemical clean Curtain coat 150 400 cps 50 mm 15 h @ 90 C 800 1,200 mJ/cm2 15 h @ 90 C Aqueous proprietary 75 min @ 35 C UV: 1.0 J/cm2 + 60 h @ 145 C 4 h @ 65 C 4 h @ 80 C 6 h @ 50 C 0.3 0.5 mm 20 h @ 90 C Product B L-PID, negative Epoxy Pumice jet Curtain coat 200 600 cps 50 mm 6 h @ 25/40 C 3 h @ 140 C 800 1,600 mJ/cm2 12 h @ 125 C Organic GBL 60 min @30 C 60 h @ 150 C Product C L-PID, negative Polyimide Br. oxide Extrusion coat 12,000 25,000 cps 37 mm 5 h @ 25 C 15 h @ 125 C 2,000 3,000 mJ/cm2 N.R. Organic proprietary 150 min @ 30 C 120 h @ 175 C Product D DF-PID, negative Epoxy Chemical clean Vac, Iam. 60 s @ 65 C 63 mm N/A 700 1,200 mJ/cm2 20 h @ 85 C Aqueous proprietary 60 min @ 35 C UV: 2 J/cm2 + 60h @ 150 C 5 h @ 60 C 10 h @ 75 C 3 h @ 25 C 0.4 mm 15 h @ 90 C

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FIGURE 22.18 Standard HDI manufacturing processes: (a) a typical photovia process with liquid resin dielectric; (b) the standard plasma via process with RCC; (c) the semiconformal laser via process; (d) the standard conductive (paste) solid via process; (e) the insulation displacement via formation process.

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